QS7001_Certifications2
Picto SEAL SQ - Fast compliance

Powerful & Fast

The SEALSQ QS7001 boasts a powerful architecture with an 80 MHz 32-bit RISC-V CPU and a dedicated cryptographic accelerator that delivers high-performance operations including post-quantum algorithms.

Picto SEAL SQ - Certifié et conforme

Certified

The SEALSQ QS7001 is certified under Common Criteria EAL5+ and supports compliance with FIPS 203 and FIPS 204, delivering advanced post‐quantum cryptography in a hardware‐based secure element.

 

 

Picto SEAL SQ - Improved security

Quantum resistant

Implements post-quantum cryptography (PQC) in hardware: specifically the NIST-standardized lattice-based algorithms CRYSTALS‑Kyber (for key-encapsulation) and CRYSTALS‑Dilithium (for digital signatures).

Picto SEAL SQ - interoperability

Flexible

The SEALSQ QS7001 has dual-interface auto-detect (I²C/SPI), GPIOs, timers and is TPM-compliant QFN32 pinout, making it easy to integrate into many hardware environments. Its open RISC-V architecture and configurable memory layout allow developers to adapt the chip to diverse secure applications with minimal redesign.

QS7001+Alpine

Hardware-level design for unmatched performance and trust

Experience exceptional speed and security with the QS7001, a powerful and versatile open hardware platform built for next-generation applications.

Built with hardware-level security that’s inherently more robust than software-only implementations, it provides enhanced performance, low latency, and reliable protection across a wide range of critical applications.

SEALSQ will highlight the launch of its new QS7001 development kit at a special event during the Las Vegas Grand Prix, showcasing how cutting-edge hardware and performance innovation intersect in both technology and motorsport.

 

 

The first ready-to-order Post-Quantum Chip

MS_600X QS 7001

Quantum Shield - QS7001

A RISC-V Secure Hardware platform offering CC EAL 5+ certified security and optimized for Kyber and Dilithium quantum resistant algorithms to face the latest attack scenarios.
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KEY FEATURES

  • 80MHz 32-bit Secured RISC-V CPU
  • CCEAL 5+ certified
  • Post Quantum: Kyber (512/768/1024) & Dilithium 2
  • RSA, ECC (572 bits), AES, DES, 3DES
  • SP 800 90 B RNG
  •  Communication: 1MBps I2C, 33MHz SPI
  • Memory: 512K Flash, 80K RAM, 128K ROM
  • 4 GPIOs, 3 Timers
  • 1,62V to 3,6V / -40° to 105° operating range
  • Package QFN32 - TPM compliant pinout
CCC
ISO 27001 (1)
Logo-partenaireNIST

The Race to Quantum Readiness

In the global race toward post-quantum readiness, precision, innovation, and speed define the leaders. Just as  BWT Alpine Formula One™ pushes engineering boundaries on the track, SEALSQ is advancing the next era of secure technology—anticipating tomorrow’s threats before they emerge. Through our Quantum Lab, we accelerate research, testing, and validation of quantum-resistant solutions, bringing cutting-edge cryptography from experimentation to real-world deployment.

The QS7001 Quantum Shield chip is the result of that commitment: a RISC-V, CC EAL5+ certified semiconductor integrating NIST-approved ML-KEM and ML-DSA algorithms directly in hardware. Purpose-built for AI, IoT, automotive, and secure edge ecosystems, it delivers robust, quantum-resistant protection today—ensuring that every device, every decision, and every data exchange remains secure in a world racing toward the quantum era.
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