The Post-Quantum Transition Has Started. 

Is Your Edge Architecture Ready?

Hardware-anchored trust. FPGA agility.
Post-quantum resilience aligned with CRA.

 

 

 
Schedule a Meeting at Embedded World 2026 Explore the Architecture
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SEAL SQ Page APPLICATIONVault IC Secure Elements

The Regulatory Clock Is Ticking.

CRA. RED. IEC 62443. ETSI.

Industrial and connected devices shipped today must remain secure, updateable, and compliant for 10–20 years.

The EU Cyber Resilience Act (CRA) and Radio Equipment Directive (RED) introduce stricter requirements around:

  • Cryptographic agility
  • Secure lifecycle management
  • Verifiable resilience
  • Post-compromise recovery
  • Wireless cybersecurity enforcement

Static security architectures are no longer sufficient.

At Embedded World 2026, we present a proof-of-concept architecture exploring how FPGA-based adaptability and TPM-based trust anchoring can be combined to support post-quantum transition and regulatory alignment.

Exploring a Dual-Anchor Architecture

 

1- TPM-Based Root of Trust Concept

 

The architecture is designed to leverage a PQC-enabled TPM to provide:

  • Standards-compliant secure boot
  • Device identity and attestation
  • Secure key provisioning and lifecycle governance
  • Policy-based authorization
  • Foundations for post-compromise recovery

This establishes the compliance-grade trust anchor required under CRA and related standards.

2-  FPGA-Based Crypto & Resilience Layer

 

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The FPGA platform demonstrates:

  • Acceleration of post-quantum cryptographic algorithms
  • Algorithm agility as standards evolve
  • Runtime mitigation concepts (rollback protection, anomaly filtering)
  • Field-updateable resilience logic

This adaptable layer enables performance and flexibility as cryptographic requirements mature.

 
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Why This POC Matters 

Modern edge platforms must balance three competing constraints: performance, long-term compliance, and cryptographic evolution.

 This proof-of-concept explores how a SEALSQ hardware Root of Trust,  whether powered by the QVault TPM or the Quantum Shield QS7001 Secure RISC-V , anchors device trust, while FPGA logic provides adaptable cryptographic execution and resilience mechanisms.

 

Trust remains anchored in principle — while security execution remains evolvable.

This architectural separation is essential for long-lifecycle industrial systems preparing for CRA compliance and post-quantum transition.

 

 

Embedded World Conference 2026 

 

🎤 Trusted Resilience at the Edge: Unified FPGA–TPM for Post-Quantum Cryptography, RED & CRA 

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SEALSQ and Lattice are presenting a conference session at Embedded World 2026:

📆 Tuesday, March 10, 2026
🕐 17:00 – 17:30
🚩 Embedded World Conference (NürnbergMesse)

Trusted Resilience Edge: Unified FPGA–TPM for Post-Quantum Cryptography, RED & Cyber Resilience Act explains how combining a hardware Root of Trust with FPGA adaptability delivers post-quantum readiness, real-time resilience, secure trust anchors, and alignment with RED and the EU Cyber Resilience Act (CRA) for long-lifecycle edge systems.

 

Hall 4, Booth #528  

 

Visit Our Dedicated PoC Corner at the Lattice Booth

The demonstration will walk through the architectural flow, secure boot concepts, PQC execution models on FPGA, crypto agility mechanisms, and the roadmap toward deeper FPGA–TPM integration.

Experts from SEALSQ and Lattice Semiconductors will be available to discuss your CRA / RED readiness, root-of-trust strategy, PQC migration planning, and FPGA–TPM co-design feasibility.

If you are evaluating next steps for compliant, post-quantum-ready edge platforms, this session is designed to provide practical architectural guidance.

Request a meeting with one of our experts and secure your time slot in advance.

 

Request a 1:1 meeting with us

Meet with our security experts.

SEALSQ × Lattice FPGA–TPM Post-Quantum PoC FAQ

Key questions and answers on architecture, value proposition, compliance alignment, and next steps.

What is the objective of this joint PoC?

 To validate technical feasibility, performance, and market interest for a unified FPGA + hardware Root of Trust architecture.
The collaboration confirms strong technical alignment and customer demand. 

Which SEALSQ chip is used?

The PoC supports both:

  • QVault TPM
  • Quantum Shield QS7001 

Depending on the architecture configuration.

Why collaborate?
  • Lattice: leader in secure, low-power FPGAs
  • SEALSQ: leader in certified post-quantum secure semiconductors

Together, we deliver hardware-anchored PQC security for FPGA-based systems.

What is the value for customers?
  • Certified hardware Root of Trust
  • Post-quantum readiness
  • Crypto-agility
  • CRA-aligned long lifecycle architecture
  • Lower BOM vs. software-only approaches
Which markets are targeted?

 Industrial, IoT, automotive, smart energy, defense, edge AI, robotics — any long-lifecycle, security-sensitive system. 

Is this aligned with regulation?

 Yes. It supports emerging cybersecurity requirements such as the EU Cyber Resilience Act (CRA) and global post-quantum transition initiatives. 

Is it commercially available?

 Currently at PoC stage.
Customer feedback at Embedded World will guide next steps toward reference boards and productization. 

Can customers evaluate it?

 Yes. Discussions can begin now. A reference board is planned. 

What role does SEALSQ play?

 SEALSQ provides the hardware Root of Trust and executes PQC operations, including authentication of FPGA bitstreams. 

How do FPGA and TPM interact?

 Via standard secure interfaces (e.g., SPI / I²C).
The FPGA handles system logic; SEALSQ hardware anchors trust and cryptography. 

Does it support hybrid cryptography?

 Yes — classical and post-quantum schemes can coexist. 

How is crypto-agility handled?

 Through firmware update mechanisms allowing algorithm evolution over time. 

Does it support secure provisioning and device identity?

 Yes — including secure key storage, authentication, and remote attestation capabilities. 

What about performance and power?

 Hardware-accelerated PQC improves efficiency versus software-only implementations and preserves FPGA resources. 

Are certifications targeted?

 Yes. SEALSQ targets FIPS and Common Criteria certifications for its hardware platforms.